1. Field of the Invention
The present invention relates to a method of forming a metallic interconnect. More particularly, the present invention relates to a method of planarizing an inter-layer dielectric (ILD) layer or inter-metal dielectric (IMD) layer using a chemical-mechanical polishing (CMP) method.
2. Description of the Prior Art
In the fabrication of semiconductors such as very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) circuits, usually two or more metallic layers are employed to interconnect semiconductor devices in different areas of a silicon chip. In general, inter-layer dielectric (ILD) or inter-metal dielectric (IMD) is used as an isolating material between metal lines in different layers. Therefore, as the design rules for forming semiconductor devices becomes highly restrictive due to miniaturization, the quality of the ILD or the IMD layer, such as its degree of surface planarity, is of growing importance.
In general, a high degree of surface planarity is an important factor in forming high-density devices using a photolithographic operation. Only a highly planar surface is capable of avoiding undesirable diffraction due to height difference during light exposure, so as to achieve a highly accurate pattern transfer. Planarization techniques can be categorized into two major groups, namely, a spin-on-glass (SOG) method and a chemical-mechanical polishing (CMP) method. However, when fabrication of semiconductors reaches the sub-half-micron stage, the spin-on-glass method is incapable of providing the degree of planarity necessary for high-quality production. Hence, the chemical-mechanical polishing method has become one of the principle means of global planarization in VLSI or ULSI production.
FIGS. 1A, 1B, 1C and 1D are cross-sectional views showing the progression of manufacturing steps in producing a metallic interconnect that uses chemical-mechanical polishing according to a conventional method. First, as shown in FIG. 1A, a semiconductor substrate 10 having an inter-layer dielectric (ILD) layer 12 thereon is provided. Then, a conductive line layer 14, for example, an aluminum layer, a metallic silicon layer, a doped polysilicon layer or a polysilicon layer is formed over the ILD layer 12. Thereafter, an insulating layer 16 is formed by deposition over the ILD layer 12 and the conductive line layer 14. Preferably, the insulating layer 16 is formed using a high-density plasma chemical vapor deposition (HDPCVD) method. Due to the presence of the conductive lines 14 underneath, the insulating layer 16 has a pyramid-like cross-sectional profile 18 near its upper surface. In the subsequent step, an inter-metal dielectric (IMD) layer 19 is formed over the insulating layer 16.
Next, as shown in FIG. 1B, a chemical-mechanical polishing (CMP) operation is carried out to polish the IMD layer 19 so that a planar upper surface is obtained. Because a CMP method can easily lead to the over-polishing of the surface of the IMD layer 19 or the scratching of surface by polishing particles, micro-scratches will appear on the surface of the IMD layer 19. These micro-scratches vary in size and depth, and two such scratches 20a and 20b are shown in FIG. 1B.
Next, as shown in FIG. 1C, conventional photolithographic and etching operations are carried out to pattern the insulating layer 16. Consequently, an opening 22 through the insulating layer 16 and the IMD layer 19 is formed. The opening 22 exposes one of the conductive line layers 14 and subsequently will serve as a via.
Next, as shown in FIG. 1D, a metallic layer 26 is formed over the IMD layer 19 and inside the opening 22. Thereafter, photolithographic and etching operations are again carried out to pattern the metallic layer 26, thereby forming second metallic lines 26. Due to the presence of scratches (20a and 20b) on the surface of the IMD layer 19, metal will also be deposited into the scratches forming undesirable metallic scratch lines 24a and 24b. 
The metallic scratch lines 24a and 24b can lead to a number of defects. FIG. 2 is a top view of a conventional metallic interconnect structure. In FIG. 2, first conductive lines 30, for example, an aluminum layer or a polysilicon layer, are formed over a semiconductor substrate (not shown in the FIGURE). In addition, second conductive lines 32 are formed above the first conductive lines 30. Through a via opening 33, the first conductive line 30 is connected to the second conductive line 32. If the surface for forming the first conductive line 30 is over-polished and scratches are formed, metallic scratch lines such as the one labeled 34 in FIG. 2 will form. The metallic scratch line can form a bridge linking up neighboring second conductive lines, thereby causing short-circuiting.
In light of the foregoing, there is a need to improve the method of the chemical-mechanical polishing operation.